Conference Impact of code density on instruction cache performance. 1989 • Conference Proceedings - Annual Symposium on Computer Architecture • 252-259 Steenkiste P
Journal Article The impact of code density on instruction cache performance 1989 • Computer architecture news • 17(3):252-259 Steenkiste P
Conference The Impact Of Code Density On Instruction Cache Performance 1989 • Proceedings / Annual International Symposium on Computer Architecture. International Symposium on Computer Architecture • 252-259 Steenkiste P
Journal Article LISP ON A REDUCED-INSTRUCTION-SET PROCESSOR - CHARACTERIZATION AND OPTIMIZATION 1988 • Computer • 21(7):34-45 STEENKISTE P, HENNESSY J
Conference A 32b microprocessor with on-chip 2Kbyte instruction cache 1987 30-31 Horowitz M, Hennessy J, Chow P, Gulak P, Acken J, Agarwal A, Chu C-Y, McFarling S, Przybylski S, Richardson S, Salz A, Simoni R, Stark D, Steenkiste P, Tjiang S, Wing M
Journal Article Tags and Type Checking in LISP: Hardware and Software Approaches 1987 • ACM Sigplan Notices • 22(10):50-59 Steenkiste P, Hennessy J
Journal Article Tags and type checking in LISP: hardware and software approaches 1987 • Computer architecture news • 15(5):50-59 Steenkiste P, Hennessy J
Conference Tags and type checking in LISP: hardware and software approaches 1987 50-59 Steenkiste P, Hennessy J
Conference TAGS AND TYPE CHECKING IN LISP: HARDWARE AND SOFTWARE APPROACHES. 1987 • Operating Systems Review • 50-59 Steenkiste P, Hennessy J
Conference LISP on a reduced-instruction-set-processor 1986 • Proceedings of the 1986 ACM Conference on LISP and Functional Programming, LFP 1986 • 192-201 Steenkiste P, Hennessy J
